SATA3H-CPUless-IP-A5ST

SATA3 Host CPUless IP Core

Design Gateway SATA3 Host CPUless IP Core is designed to be an all-in-one system containing the application, transport, and link layers in one IP. This helps the connection with the PHY layer implemented by the transceiver without CPU and DDR usage. The SATA Physical layer is designed using an HDL code to control the transceiver following the SATA protocol. The interface module is connected between the SATA3H-CL IP and the SATA device. This SATA3 IP core PHY is provided in the reference design in the release stuff for the IP customer. The SATA3 host IP core features a dgIF typeS user interface that is very easy to access and comes with a control and data interface.