LMK1D1212RHAR

LMK1D121x Low Additive Jitter LVDS Clock Buffer

Texas Instruments LMK1D121x Low Additive Jitter LVDS Clock Buffer is specifically designed for driving 50Ω transmission lines. When driving inputs in single-ended mode, apply the appropriate bias voltage to the unused negative input pin. The LMK1D1212 distributes with minimum skew one of two selectable clock inputs (IN0 and IN1) to 12 pairs of differential LVDS clock outputs (OUT0 through OUT11). Similarly, the LMK1D1216 distributes 16 pairs of differential LVDS clock outputs (OUT0 through OUT15). The LMK1D121x family can accept two clock sources into an input multiplexer. The inputs can be LVDS, LVPECL, LP-HCSL, HCSL, CML, or LVCMOS.